The existing silicon-based Integrated Circuit (IC) technology follows Moore's Law to improve performances by scaling down, which will bring about the complexity of equipments and processes. Especially when the semiconductor technology is developed to the nanometer scale, the silicon-based IC technology is increasingly approaching both theoretic and technical limits. The use of new materials and new device structures to continue to improve the performances of CMOS devices has become an important research trend. Group III-V semiconductors have higher electron mobility and very good transport properties in either a low electric field or a strong field, and thus become a current research hotspot. In addition, the group III-V semiconductors have a series of lattice-matched heterojunction material systems, and thus both energy band engineering and impurity engineering can be flexibly applied while designing the devices. However, for InGaAs-based PMOS devices, due to the lower hole mobility, there are still some problems to be solved to achieve high performance PMOS devices. At a surface of the group III-V semiconductor, it is needed to reduce the MOS interface state density to improve the carrier mobility in the channel. However, it is difficult for the traditional device structure to meet the requirements of high performance.
Therefore, there is a need for a new method and structure to achieve high performance InGaAs-based PMOS devices to meet the requirements of the group III-V CMOS technology.